參數資料
型號: SP3223EUEY-L
廠商: Exar Corporation
文件頁數: 3/20頁
文件大?。?/td> 0K
描述: IC TXRX RS232 INTELLIGNT 20TSSOP
標準包裝: 74
類型: 收發(fā)器
驅動器/接收器數: 2/2
規(guī)程: RS232
電源電壓: 3 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 管件
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (50)668-707 www.exar.com
SP3223E/EB/EU_0_06272
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
outputvoltages exceedamagnitudeof5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V
SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tors C
and C2 are initially charged to VCC.
C
l
+
is then switched to GND and the charge
in C
is transferred to C
2
. Since C
2
+
is con-
nected to V
CC, the voltage potential across
capacitor C
2 is now 2 times VCC.
Phase 2
— V
SS transfer — Phase two of the clock
connectsthenegativeterminalofC
2 to the VSS
storagecapacitorandthepositiveterminalof
C
2 to GND. This transfers a negative gener-
ated voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C
3, the positive side of capacitor C
is switched to V
CC and the negative side is
connected to GND.
Phase 3
— V
DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C
produces –VCC in
the negative terminal of C
, which is applied
to the negative side of capacitor C
2. Since
C
2
+
is at V
CC, the voltage potential across C2
is 2 times V
CC.
Phase 4
— V
DD transfer — The fourth phase of
the clock connects the negative terminal
of C
2 to GND, and transfers this positive
generated voltage across C
2 to C4, the
V
DD storage capacitor.
This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
4, the
positivesideofcapacitorC
is switched to VCC
and the negative side is switched to GND, al-
lowingthechargepumpcycletobeginagain.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
Since both V+ and Vare separately gener-
ated from V
CC, in a no–load condition V
+
and Vwill be symmetrical. Older charge
pump approaches that generate Vfrom
V+ will show a decrease in the magnitude
of Vcompared to V+ due to the inherent
inefficiencies in the design.
The Exar charge pump is designed to
operate reliably with a range of low cost
capacitors. Either polarized or non polar-
ized capacitors may be used. If polarized
capacitors are used they should be oriented
as shown in the Typical Operating Circuit.
TheV+capacitormaybeconnectedtoeither
ground or Vcc (polarity reversed.)
The charge pump operates with 0.F
capacitors for 3.3V operation. For other
supply voltages, see table 4 for required
capacitor values. Do not use values smaller
than those listed. Increasing the capacitor
values (e.g., by doubling in value) reduces
ripple on the transmitter outputs and may
slightly reduce power consumption. C2, C3,
and C4 can be increased without changing
C’s value.
For best charge pump efficiency locate the
charge pump and bypass capacitors as
close as possible to the IC. Surface mount
capacitors are best for this purpose. Using
capacitors with lower equivalent series re-
sistance (ESR) and self-inductance, along
with minimizing parasitic PCB trace induc-
tance will optimize charge pump operation.
Designers are also advised to consider that
capacitor values may shift over time and
operating temperature.
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