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參數(shù)資料
| 型號： | SNJ54LVTH540J |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 485K |
| 代理商： | SNJ54LVTH540J |
SN54LVTH540, SN74LVTH540
3.3V ABT OCTAL BUFFERS/DRIVERS
WITH 3STATE OUTPUTS
SCBS681G MARCH 1997 REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
INPUTS
OUTPUT
OE1
OE2
A
OUTPUT
Y
L
H
L
LH
L
H
XX
Z
X
H
X
Z
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1
Y1
1
19
218
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