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參數(shù)資料
| 型號： | SNJ54LVTH126W |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 582K |
| 代理商： | SNJ54LVTH126W |
SN54LVTH126, SN74LVTH126
3.3V ABT QUADRUPLE BUS BUFFERS
WITH 3STATE OUTPUTS
SCBS746B JULY 2000 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
H
LL
L
X
Z
logic diagram (positive logic)
1
1OE
2
1A
1Y
3
4
2OE
5
2A
2Y
6
10
3OE
9
3A
3Y
8
13
4OE
12
4A
4Y
11
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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