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參數(shù)資料
| 型號(hào)： | SNJ54LV164AW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 814K |
| 代理商： | SNJ54LV164AW |
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated
serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data
and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,
which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock
is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of the clock (CLK) input.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
A
B
QA
QB ...QH
L
X
L
H
LX
X
QA0
QB0
QH0
H
↑
HH
H
QAn
QGn
H
↑
LX
L
QAn
QGn
H
↑
X
L
QAn
QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock: indicates a 1-bit shift.
logic diagram (positive logic)
C1
1D
R
C1
1D
R
QA
QB
C1
1D
R
C1
1D
R
QC
QD
C1
1D
R
C1
1D
R
QE
QF
C1
1D
R
C1
1D
R
QG
QH
345
6
10
11
12
13
8
1
2
9
CLK
A
B
CLR
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
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