參數(shù)資料
型號(hào)： SNJ54LV161AJ
廠商： TEXAS INSTRUMENTS INC
元件分類： 計(jì)數(shù)器
英文描述： LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
封裝： CERAMIC, DIP-16
文件頁(yè)數(shù)： 12/24頁(yè)
文件大小： 687K
代理商： SNJ54LV161AJ
SN54LV161A, SN74LV161A
4BIT SYNCHRONOUS BINARY COUNTERS
SCLS404F APRIL 1998 REVISED DECEMBER 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and
internal gating. This mode of operation eliminates the output counting spikes that normally are associated with
synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four
of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
LOAD
ENP
ENT
CLK
QA
QB
QC
QD
FUNCTION
L
X
L
Reset to “0”
H
LX
X
↑
A
B
C
D
Preset Data
H
HX
L
↑
No Change
No Count
H
HL
X
↑
No Change
No Count
H
HH
H
↑
Count up
Count
H
X
↑
No Change
No Count
相關(guān)PDF資料
PDF描述
SN74LV161ADRG4 LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SNJ54LV163AJ LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
SN74LV163ANSRE4 LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SN74LV163APWE4 LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SN74LV163ADBR LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
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