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參數(shù)資料
| 型號： | SNJ54ALS174FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | ALS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 729K |
| 代理商： | SNJ54ALS174FK |
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = –18 mA
–1.5
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = –0.4 mA
VCC– 2
V
VOL
VCC =4 5V
IOL = 4 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = 4.5 V
IOL = 8 mA
0.35
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
A
IIL
All others
VCC =5 5V
VI =0 4V
–0.1
mA
IIL
CLK
VCC = 5.5 V,
VI = 0.4 V
–0.15
mA
IO
VCC = 5.5 V,
VO = 2.25 V
–20
–112
–30
–112
mA
ICC
’ALS174
VCC =5 5V
See Note 3
11
19
11
19
mA
ICC
’ALS175
VCC = 5.5 V,
See Note 3
8
14
9
14
mA
All typical values are at VCC = 5 V, TA = 25°C.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 3: ICC is measured with D inputs and CLR grounded, and CLK at 4.5 V.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
40
50
MHz
CLR low
15
10
tw
Pulse duration
CLK high
12.5
10
ns
CLK low
12.5
10
t
Set p time before CLK
↑
Data
15
10
ns
tsu
Setup time before CLK
↑
CLR inactive
8
6
ns
th
Hold time, data after CLK
↑
0
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 ,
TA = MIN to MAX§
UNIT
PARAMETER
(INPUT)
(OUTPUT)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
MAX
MIN
MAX
fmax
40
50
MHz
tPLH
CLR
Any Q
3
20
5
18
ns
tPHL
CLR
y
(or Q, ’ALS175)
5
30
8
23
ns
tPLH
CLK
Any Q
3
20
3
15
ns
tPHL
CLK
y
(or Q, ’ALS175)
5
24
5
17
ns
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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| SN74ALS175DG4 | ALS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SNJ54ALS174J | 制造商:Texas Instruments 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin CDIP Tube |
| SNJ54ALS174W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| SNJ54ALS175FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| SNJ54ALS175J | 制造商:Texas Instruments 功能描述: |
| SNJ54ALS175W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
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