參數(shù)資料
型號: SN75LVDS83CZQLR
廠商: Texas Instruments
文件頁數(shù): 5/27頁
文件大?。?/td> 0K
描述: IC FLATLINK TX 10-85MHZ 56BGA
標(biāo)準(zhǔn)包裝: 1,000
系列: *
SLLSE66A
– OCTOBER 2010 – REVISED SEPTEMBER 2011
APPLICATION INFORMATION
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a pcb routing example.
Power Up Sequence
The SN75LVDS83C does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN75LVDS83C SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won
’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83C shutdown to SHTDN = VIH.
5. Send
>1ms of black video data; this allows the LVDS83C to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS83C SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for
>2 frame times.
3. Set SN75LVDS83C input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 11 through Figure 14 show how
each signal should be connected from the graphic source through the SN75LVDS83C input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.
Copyright
2010–2011, Texas Instruments Incorporated
13
Product Folder Link(s): SN75LVDS83C
相關(guān)PDF資料
PDF描述
SP3220EUEA-L/TR IC DVR/RCVR RS232 ESD 16SSOP
SP3226EEA-L IC TXRX RS232 ESD SD 16SSOP
SP3244EER1-L IC TXRX RS232 32QFN
SP336EEY-L/TR IC TXRX RS232/485 PROG 28TSSOP
SP491ES-L IC TXRX RS485 FULL DUPLEX 14PDIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN75LVDS83DGG 功能描述:總線發(fā)射器 Flatlink RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:135 Mpps 接口: 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-56 封裝:Reel
SN75LVDS83DGG 制造商:Texas Instruments 功能描述:IC FLATLINK(TM) XMITTER 56-TSSOP 制造商:Texas Instruments 功能描述:IC, FLATLINK(TM) XMITTER 56-TSSOP 制造商:Texas Instruments 功能描述:IC, FLATLINK(TM) XMITTER 56-TSSOP; MSL:MSL 2 - 1 year; SVHC:No SVHC (19-Dec-2012); Base Number:75; Device Type:LVDS; No. of Pins:56; Operating Temperature Max:70C; Operating Temperature Min:0C; Operating Temperature Range:0C to ;RoHS Compliant: Yes
SN75LVDS83DGG 制造商:Texas Instruments 功能描述:SEMICONDUCTOR
SN75LVDS83DGGG4 功能描述:總線發(fā)射器 Flatlink RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:135 Mpps 接口: 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-56 封裝:Reel
SN75LVDS83DGG-P 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: