參數(shù)資料
型號: SN74SSTVF16857VR
廠商: TEXAS INSTRUMENTS INC
元件分類: 鎖存器
英文描述: SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
封裝: GREEN, PLASTIC, TVSOP-48
文件頁數(shù): 8/12頁
文件大?。?/td> 341K
代理商: SN74SSTVF16857VR
SN74SSTVF16857
14BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES411B – AUGUST 2002 – REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 2.6 V
± 0.1 V
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
250
MHz
tw
Pulse duration, CLK, CLK high or low
2
ns
tact
Differential inputs active time (see Note 5)
22
ns
tinact
Differential inputs inactive time (see Note 6)
22
ns
t
Set p time
Fast slew rate (see Notes 7 and 9)
Dt bf
CLK
↑ CLK↓
0.75
ns
tsu
Setup time
Slow slew rate (see Notes 8 and 9)
Data before CLK
↑, CLK↓
0.9
ns
th
Hold time
Fast slew rate (see Notes 7 and 9)
Data after CLK
↑ CLK↓
0.75
ns
th
Hold time
Slow slew rate (see Notes 8 and 9)
Data after CLK
↑, CLK↓
0.9
ns
For this test condition, VDDQ always is equal to VCC.
NOTES:
5. VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
6. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken
low.
7. For data signal input slew rate
≥1 V/ns.
8. For data signal input slew rate
≥0.5 V/ns and <1 V/ns.
9. CLK, CLK signals input slew rates are
≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
VCC = 2.6 V
± 0.1 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
250
MHz
tpd
CLK and CLK
Q
1.1
2.6
1.1
2.6
ns
tPHL
RESET
Q
5
ns
For this test condition, VDDQ always is equal to VCC.
Single bit switching
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