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參數(shù)資料
| 型號(hào)： | SN74SSTV32867GKER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | PLASTIC, LFBGA-96 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | SN74SSTV32867GKER |
SN74SSTV32867
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES362B – OCTOBER 2001 – REVISED MAY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VIK
II = –18 mA
2.3 V
–1.2
V
VOH
IOH = –100 A
2.3 V to 2.7 V
VDDQ–0.2
V
VOH
IOH = –8 mA
2.3 V
1.7
V
VOL
IOL = 100 A
2.3 V to 2.7 V
0.2
V
VOL
IOL = 8 mA
2.3 V
0.4
V
II
All inputs
VI = VCC or GND
2.7 V
±5
A
Static standby
RESET = GND
40
A
ICC
Static operating
RESET = VCC,
VI = VIH(AC) or VIL(AC)
IO = 0
2.7 V
95
mA
Dynamic
operating –
clock only
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching
50% duty cycle
44
A/
MHz
ICCD
Dynamic
operating –
per each data
input
RESET = VCC,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching
50% duty cycle,
One data input switching at
one-half clock frequency,
50% duty cycle
IO = 0
2.5 V
5
A/
clock
MHz/
D input
Data inputs
VI = VREF ± 310 mV
2.5
3.5
4.5
Ci
CLK, CLK
VICR = 1.25 V,
VI(PP) = 360mV
2.5 V
4
4.5
5
pF
RESET
VI = VCC or GND
3.9
5
5.5
All typical values are at VCC = 2.5 V, TA = 25°C.
Measured with 50-MHz input frequency
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
UNIT
MIN
MAX
fclock Clock frequency
200
MHz
tw
Pulse duration
CLK, CLK high or low
2.5
ns
tact
Differential inputs active time (see Note 5)
22
ns
tinact Differential inputs inactive time (see Note 6)
22
ns
t
Setup time
Fast slew rate (see Notes 7 and 9)
Dt bf
CLK
↑ CLK↓
0.75
ns
tsu
Setup time
Slow slew rate (see Notes 8 and 9)
Data before CLK
↑, CLK↓
0.9
ns
th
Hold time
Fast slew rate (see Notes 7 and 9)
Data after CLK
↑ CLK↓
0.75
ns
th
Hold time
Slow slew rate (see Notes 8 and 9)
Data after CLK
↑, CLK↓
0.9
ns
NOTES:
5. Data inputs must be low a minimum time of tact min, after RESET is taken high.
6. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact min, after RESET is taken low.
7. Data signal input slew rate
≥1 V/ns
8. Data signal input slew rate
≥0.5 V/ns and <1 V/ns
9. CLK, CLK input slew rates are
≥1 V/ns.
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