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參數(shù)資料
| 型號(hào)： | SN74SSTU32864GKER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | PLASTIC, LFBGA-96 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 561K |
| 代理商： | SN74SSTU32864GKER |
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS
or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR
control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired
to ground, in which case, the setup-time requirement for DCS is the same as for the other D data inputs.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
terminal assignments for 1:1 register (C0 = 0, C1 = 0)
1
2345
6
A
D1 (DCKE)
NC
VREF
VCC
Q1 (QCKE)
DNU
B
D2
D15
GND
Q2
Q15
C
D3
D16
VCC
Q3
Q16
D
D4 (DODT)
NC
GND
Q4 (QODT)
DNU
E
D5
D17
VCC
Q5
Q17
F
D6
D18
GND
Q6
Q18
G
NC
RESET
VCC
C1
C0
H
CLK
D7 (DCS)
GND
Q7 (QCS)
DNU
J
CLK
CSR
VCC
NC
K
D8
D19
GND
Q8
Q19
L
D9
D20
VCC
Q9
Q20
M
D10
D21
GND
Q10
Q21
N
D11
D22
VCC
Q11
Q22
P
D12
D23
GND
Q12
Q23
R
D13
D24
VCC
Q13
Q24
T
D14
D25
VREF
VCC
Q14
Q25
Each pin name in parentheses indicates the DDR-II DIMM signal name.
NC – No internal connection
DNU – Do not use
GKE PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
13
4
6
5
P
N
M
L
K
T
R
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