參數(shù)資料
型號: SN74LVTT240PWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 1/6頁
文件大?。?/td> 106K
代理商: SN74LVTT240PWLE
SN54LVTT240, SN74LVTT240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES005 – FEBRUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
Supports Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Supports Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
These octal buffers and line drivers are designed
specifically for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface to
a 5-V system environment.
The ’LVTT240 is organized as two 4-bit buffer/line
drivers with separate output-enable (OE) inputs.
When OE is low, the device passes data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVTT240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVTT240 is characterized for operation over the full military temperature range of – 55
°C to 125°C.
The SN74LVTT240 is characterized for operation from – 40
°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
Y
L
H
L
LH
H
X
Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LVTT240 ...J OR W PACKAGE
SN74LVTT240 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54LVTT240 . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2
2OE
2Y1
GND
2A1
V
CC
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
相關(guān)PDF資料
PDF描述
SN54LVTT240FK LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CQCC20
SN74LVTT240DWR LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
SN74LVTT240J LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20
SN54LVTT240DWR LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
SNJ54LVTT240DBLE LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
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