- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98089 > SN74LVTH543DGV (TEXAS INSTRUMENTS INC) LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 PDF資料下載
參數(shù)資料
| 型號： | SN74LVTH543DGV |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | PLASTIC, TVSOP-24 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SN74LVTH543DGV |
Product Folder: SN74LVTH543, 3.3-V ABT Octal Registered Transceivers With 3-State Outputs
PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG | SAMPLES
PRODUCT SUPPORT: TRAINING
SN74LVTH543, 3.3-V ABT Octal Registered Transceivers With 3-State Outputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN74LVTH543
Voltage Nodes (V) 3.3, 2.7
FEATURES
q
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
q
Ioff and Power-Up 3-State Support Hot Insertion
q
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
q
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
q
Support Unregulated Battery Operation Down to 2.7 V
q
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
q
Latch-Up Performance Exceeds 500 mA Per JESD 17
q
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
q
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Ceramic (JT) DIPs
DESCRIPTION
These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The 'LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\)
inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high
transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow
from B to A is similar, but requires using the CEBA\, LEBA\, and OEBA\ inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is
powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
The SN54LVTH543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH543 is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
To view the following documents, Acrobat Reader 4.0 is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
file:///H|/imaging/BITTING/cpl/20020930_1/09272002_10/TXII/09272002_HTML/sn74lvth543.html (1 of 4) [Oct-05-2002 11:55:50 AM]
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH573J | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| SN54LVTH573FK | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20 |
| SN54LVTH646JT | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24 |
| SN54LVTH652FK | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| SN74LVTH652DGV | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVTH543DGVR | 功能描述:總線收發(fā)器 Tri-State ABT Octal RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH543DGVRE4 | 功能描述:總線收發(fā)器 Single-Supply Voltage Translator RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH543DGVRG4 | 功能描述:總線收發(fā)器 3.3V ABT Octal Registred Transceivr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH543DW | 功能描述:總線收發(fā)器 Tri-State ABT Octal RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH543DWE4 | 功能描述:總線收發(fā)器 3.3V ABT Octal Reg Trncvr W/3-St Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。