參數(shù)資料
型號: SN74LVTH240PWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 12/22頁
文件大?。?/td> 767K
代理商: SN74LVTH240PWLE
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K DECEMBER 1996 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
terminal assignments
1234
A
1A1
1OE
VCC
2OE
B
1A2
2A4
2Y4
1Y1
C
1A3
2Y3
2A3
1Y2
D
1A4
2A2
2Y2
1Y3
E
GND
2Y1
2A1
1Y4
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
L
LH
H
X
Z
SN74LVTH240 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1
234
A
B
C
D
E
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SN74LVTH240DBLE LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
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