- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98127 > SN74LVTH182514DGG (TEXAS INSTRUMENTS INC) LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64 PDF資料下載
參數(shù)資料
| 型號： | SN74LVTH182514DGG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64 |
| 封裝： | PLASTIC, TSSOP-64 |
| 文件頁數(shù)： | 30/34頁 |
| 文件大?。?/td> | 548K |
| 代理商： | SN74LVTH182514DGG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS670C – AUGUST 1996 – REVISED MARCH 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Std 1149.1-1990.
Test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus: TCK and TMS. The TAP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture
and the relationships of the test bus, the TAP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test data registers: a 48-bit boundary-scan register, a 3-bit boundary-control
register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LVTH18514DGG | LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64 |
| SN74LVTH18640DL | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74LVTH18640DGGR | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
| SN74LVTH2245DBRE4 | LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20 |
| SN74LVTH2245DBR | LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVTH182646APM | 功能描述:特定功能邏輯 18bit ABT 3.3V RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH182652APM | 功能描述:特定功能邏輯 10-Bit Bus Interface F-F W/3-State Otpt RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18502APM | 功能描述:特定功能邏輯 3.3-V ABT w/18-Bit Univ Bus Transceiver RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18502APMG4 | 功能描述:特定功能邏輯 3.3-V ABT w/18-Bit Univ Bus Transceiver RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18502APMR | 功能描述:特定功能邏輯 10-Bit Bus/MOS Mem Drv RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。