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參數(shù)資料
| 型號： | SN74LVT16245BZRDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA54 |
| 封裝： | GREEN, PLASTIC, LFBGA-54 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 618K |
| 代理商： | SN74LVT16245BZRDR |
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3 4
6
5
K
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS715E – FEBRUARY 2000 – REVISED NOVEMBER 2006
The 'LVT16245B devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between two data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
1
2
3
4
5
6
A
1DIR
NC
1OE
B
1B2
1B1
GND
1A1
1A2
C
1B4
1B3
VCC
1A3
1A4
D
1B6
1B5
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
2A4
2A3
H
2B5
2B6
VCC
2A6
2A5
J
2B7
2B8
GND
2A8
2A7
K
2DIR
NC
2OE
(1)
NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
A
1B1
NC
1DIR
1OE
NC
1A1
B
1B3
1B2
NC
1A2
1A3
C
1B5
1B4
VCC
1A4
1A5
D
1B7
1B6
GND
1A6
1A7
E
2B1
1B8
GND
1A8
2A1
F
2B3
2B2
GND
2A2
2A3
G
2B5
2B4
VCC
2A4
2A5
H
2B7
2B6
NC
2A6
2A7
J
2B8
NC
2DIR
2OE
NC
2A8
(1)
NC – No internal connection
2
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