參數(shù)資料
型號： SN74LVT125QDREP
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝： SOIC-14
文件頁數(shù)： 7/11頁
文件大?。?/td> 311K
代理商： SN74LVT125QDREP
www.ti.com
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPLH
VOH
VOL
1.5 V
2.7 V
0 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
SN74LVT125-EP
3.3-V ABT QUADRUPLE BUS BUFFER
WITH 3-STATE OUTPUTS
SCBS796A – JANUARY 2004 – REVISED JUNE 2005
Figure 1. Load Circuit and Voltage Waveforms
5
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