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參數(shù)資料
| 型號(hào)： | SN74LVCH16373ADGVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | GREEN, PLASTIC, TVSOP-48 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 503K |
| 代理商： | SN74LVCH16373ADGVR |
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3 4
6
5
K
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006
The SN74LVCH16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
1
2
3
4
5
6
A
1OE
NC
1LE
B
1Q2
1Q1
GND
1D1
1D2
C
1Q4
1Q3
VCC
1D3
1D4
D
1Q6
1Q5
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
2D4
2D3
H
2Q5
2Q6
VCC
2F6
2D5
J
2Q7
2Q8
GND
2D8
2D7
K
2OE
NC
2LE
XXXXXXX
(1)
NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
A
1Q1
NC
1OE
1LE
NC
1D1
B
1Q3
1Q2
NC
1D2
1D3
C
1Q5
1Q4
VCC
1D4
1D5
D
1Q7
1Q6
GND
1D6
1D7
E
2Q1
1Q8
GND
1D8
2D1
F
2Q3
2Q2
GND
2D2
2D3
G
2Q5
2Q4
VCC
2D4
2D5
H
2Q7
2Q6
NC
2D6
2D7
J
2Q8
NC
2OE
2LE
NC
2D8
(1)
NC – No internal connection
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVCH16373ADL | 功能描述:閉鎖 Tri-St. 16bit D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVCH16373ADLG4 | 功能描述:閉鎖 Tri-St. 16bit D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVCH16373ADLR | 功能描述:閉鎖 Tri-St. 16bit D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVCH16373AGQLR | 功能描述:閉鎖 Tri-St. 16bit D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVCH16373AGRDR | 功能描述:閉鎖 SN74LVCH16373A RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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