參數(shù)資料
型號(hào): SN74LVC86APWG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 門(mén)電路
英文描述: LVC/LCX/Z SERIES, QUAD 2-INPUT XOR GATE, PDSO14
封裝: GREEN, PLASTIC, TSSOP-14
文件頁(yè)數(shù): 17/23頁(yè)
文件大?。?/td> 926K
代理商: SN74LVC86APWG4
www.ti.com
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Output voltage range(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
D package (4)
86
DB package(4)
96
θ
JA
Package thermal impedance
NS package(4)
76
°C/W
PW package(4)
113
RGY package(4)
47
Tstg
Storage temperature range
–65
150
°C
Ptot
Power dissipation
TA = –40°C to 125°C(5)(6)
500
mW
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
For the D package: above 70
°C, the value of P
tot derates linearly with 8 mW/K.
(6)
For the DB, DGV, NS, and PW packages: above 60
°C, the value of P
tot derates linearly with 5.5 mW/K.
SN54LVC86A
–55 TO 125
°C
UNIT
MIN
MAX
Operating
2
3.6
VCC
Supply voltage
V
Data retention only
1.5
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V
–12
IOH
High-level output current
mA
VCC = 3 V
–24
VCC = 2.7 V
12
IOL
Low-level output current
mA
VCC = 3 V
24
t/v
Input transition rise or fall rate
9
ns/V
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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