參數(shù)資料
型號： SN74LVC74APWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： GREEN, PLASTIC, TSSOP-14
文件頁數(shù)： 15/21頁
文件大?。?/td> 784K
代理商： SN74LVC74APWR
www.ti.com
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Output voltage range(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
D package(4)
86
DB package(4)
96
θ
JA
Package thermal impedance
NS package(4)
76
°C/W
PW package(4)
113
RGY package(5)
47
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LVC74A
SN74LVC74A
UNIT
MIN
MAX
MIN
MAX
Operating
2
3.6
1.65
3.6
VCC
Supply voltage
V
Data retention only
1.5
VCC = 1.65 V to 1.95 V
0.65 × VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V
0.8
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
IOH
High-level output current
mA
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
IOL
Low-level output current
mA
VCC = 2.7 V
12
VCC = 3 V
24
t/v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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