參數(shù)資料
型號(hào)： SN74LVC2GU04YEPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 門電路
英文描述： LVC/LCX/Z SERIES, DUAL 1-INPUT INVERT GATE, PBGA6
封裝： DSBGA-6
文件頁(yè)數(shù)： 8/14頁(yè)
文件大小： 403K
代理商： SN74LVC2GU04YEPR
www.ti.com
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
DUAL INVERTER GATE
SCES197L – APRIL 1999 – REVISED AUGUST 2006
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
DBV package
165
DCK package
259
θ
JA
Package thermal impedance(4)
°C/W
YEA/YZA package
143
YEP/YZP package
123
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
VCC
Supply voltage
1.65
5.5
V
VIH
High-level input voltage
IO = –100 A
0.75
× V
CC
V
VIL
Low-level input voltage
IO = 100 A
0.25
× V
CC
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
IOH
High-level output current
–16
mA
VCC = 3 V
–24
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
IOL
Low-level output current
16
mA
VCC = 3 V
24
VCC = 4.5 V
32
TA
Operating free-air temperature
–40
85
°C
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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