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參數(shù)資料
| 型號(hào)： | SN74LVC16646ADL |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | GREEN, PLASTIC, SSOP-56 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | SN74LVC16646ADL |
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B – AUGUST 2002 – REVISED APRIL 2005
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with
the SN74LVC16646A.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and
SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control
eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and
real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data
can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O(1)
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1-A8
B1-B8
X
↑
X
Input
Unspecified
Store A, B unspecified(1)
X
↑
X
Unspecified
Input
Store B, A unspecified(1)
H
X
↑
X
Input
Store A and B data
H
X
H or L
X
Input
Isolation, hold storage
L
X
L
Output
Input
Real-time B data to A bus
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
(1)
The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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| SN74LVC16646ADLG4 | 功能描述:總線收發(fā)器 16B Bus Transceiver And Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVC16646ADLR | 功能描述:總線收發(fā)器 16BBusTrans Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVC16646ADLRG4 | 功能描述:總線收發(fā)器 16B Bus Transceiver And Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVC16646DL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74LVC16652DL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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