參數(shù)資料
型號(hào): SN74LVC00APWTG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: GREEN, PLASTIC, TSSOP-14
文件頁(yè)數(shù): 18/24頁(yè)
文件大?。?/td> 920K
代理商: SN74LVC00APWTG4
www.ti.com
Absolute Maximum Ratings
(1)
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279P – JANUARY 1993 – REVISED JULY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Output voltage range(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
VCC
Continuous current through GND
±100
mA
D package(4)
86
DB package(4)
96
θ
JA
Package thermal impedance
NS package(4)
76
°C/W
PW package(4)
113
RGY package(5)
47
Tstg
Storage temperature range
–65
150
°C
Ptot
Power dissipation(6)(7)
TA = –40°C to 125°C
500
mW
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
The package thermal impedance is calculated in accordance with JESD 51-5.
(6)
For the D package: above 70
°C, the value of P
tot derates linearly with 8 mW/K.
(7)
For the DB, NS, and PW packages: above 60
°C, the value of P
tot derates linearly with 5.5 mW/K.
3
相關(guān)PDF資料
PDF描述
SN74LVC00APWR LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
SN74LVC00AMPWREP LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
SN74LVC02ANSRE4 LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14
SN74LVC04APWT LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
SN74LVC04ARGYR LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PQCC14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LVC00AQDREP 功能描述:邏輯門 Mil Enhance Quad 2 Input Pos-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
SN74LVC00AQDRG4Q1 功能描述:邏輯門 Quad 2-Inp Pos-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
SN74LVC00AQDRQ1 功能描述:邏輯門 Auto Cat Qud 2 Input Positive NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
SN74LVC00AQPWREP 功能描述:邏輯門 Mil Enhance Quad 2 Input Pos-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
SN74LVC00AQPWRG4Q1 功能描述:邏輯門 Quad 2-Inp Pos-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel