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| 型號(hào)： | SN74LV8153PWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 385K |
| 代理商： | SN74LV8153PWRG4 |
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SN74LV8153
SERIALTOPARALLEL INTERFACE
SCLS555 JUNE 2004
www.ti.com
3
data transmission protocol
The serial data should be sent as 2START-3ADDRESS-4DATA-1STOP. Two consecutive serial-data
frames transmit 8 bits of data. The first frame includes the lower four bits of data (D0-D3), and the
second frame includes the upper four bits (D4-D7).
The three address bits (in the consecutive frame) must be the same as those in the first frame;
otherwise, the data will be dropped.
The order of the two start bits must be 0, then 1 in any frame; otherwise, the data rate will not be
detected correctly. The period between the falling edge of the first start bit (ST0) and the rising edge of
the second start bit (ST1) is measured to generate an internal-clock synchronized data stream.
1st Frame
2nd Frame
DATA
Internal Clock
Y0Y7
SOUT
Timing Chart
Example of Serial-Data Format
ST0
ST1
A0
A1
A2
D0
D1
D2
D3
SP
ST0
ST1
A0
A1
A2
D4
D5
D7
SP
D6
ST0
ST1
A0
A1
A2
D0
D1
D2
D3
SP
ST0
ST1
A0
A1
A2
D4
D5
D7
SP
D6
(1)Internal clock cannot be observed.
(2)D0 is LSB and D7 is MSB. The data stream should be LSB first.
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