參數(shù)資料
型號: SN74LV595ANSRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 計數(shù)移位寄存器
英文描述: LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: GREEN, PLASTIC, SOP-16
文件頁數(shù): 25/26頁
文件大?。?/td> 848K
代理商: SN74LV595ANSRG4
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O APRIL 1998 REVISED JANUARY 2011
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV595A
SN74LV595A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
SRCLK high or low
5.5
tw
Pulse duration
RCLK high or low
5.5
ns
tw
Pulse duration
SRCLR low
5
ns
SER before SRCLK↑
3.5
t
Setup time
SRCLK↑ before RCLK↑
8
8.5
ns
tsu
Setup time
SRCLR low before RCLK↑
8
9
ns
SRCLR high (inactive) before SRCLK↑
3
th
Hold time
SER after SRCLK↑
1.5
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV595A
SN74LV595A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
SRCLK high or low
5
tw
Pulse duration
RCLK high or low
5
ns
tw
Pulse duration
SRCLR low
5.2
ns
SER before SRCLK↑
3
t
Setup time
SRCLK↑ before RCLK↑
5
ns
tsu
Setup time
SRCLR low before RCLK↑
5
ns
SRCLR high (inactive) before SRCLK↑
2.5
th
Hold time
SER after SRCLK↑
2
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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