參數(shù)資料
型號(hào)： SN74LV273ADBLE
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 7/11頁(yè)
文件大?。?/td> 200K
代理商： SN74LV273ADBLE
SN54LV273A, SN74LV273A
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS399B – APRIL 1998 – REVISED MAY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV273A
SN74LV273A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
6.5
7
ns
tw
Pulse duration
CLK high or low
7
8.5
ns
t
Set p time data before CLK
↑
Data
8.5
10.5
ns
tsu
Setup time, data before CLK
↑
CLR inactive
4
ns
th
Hold time, data after CLK
↑
0.5
1
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV273A
SN74LV273A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
6
ns
tw
Pulse duration
CLK high or low
5
6.5
ns
t
Set p time data before CLK
↑
Data
5.5
6.5
ns
tsu
Setup time, data before CLK
↑
CLR inactive
2.5
ns
th
Hold time, data after CLK
↑
1
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV273A
SN74LV273A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
5
ns
t
Set p time data before CLK
↑
Data
4.5
ns
tsu
Setup time, data before CLK
↑
CLR inactive
2
ns
th
Hold time, data after CLK
↑
1
ns
switching
characteristics
over
recommended
operating
free-air
temperature
range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
SN54LV273A
SN74LV273A
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
55*
95*
45*
45
MHz
fmax
CL = 50 pF
45
75
40
MHz
tpd
CLK
Q
CL =15 pF
10.4*
18.3*
1*
20.5*
1
20.5
ns
tPHL
CLR
Q
CL = 15 pF
10.3*
19*
1*
21*
1
21
ns
tpd
CLK
Q
12.9
22.1
1
25
1
25
tPHL
CLR
Q
CL = 50 pF
13.1
22.8
1
25.5
1
25.5
ns
tsk(o)
2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LV273ADBR 功能描述:觸發(fā)器 Octal w/ Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LV273ADBRE4 功能描述:觸發(fā)器 Octal D-Type Flip-Flop w/Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LV273ADBRG4 功能描述:觸發(fā)器 Octal DType FlipFlop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LV273ADGVR 功能描述:觸發(fā)器 Octal w/ Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LV273ADGVRE4 功能描述:觸發(fā)器 Octal D-Type Flip-Flop w/Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
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