參數(shù)資料
型號: SN74LV125APWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: GREEN, PLASTIC, TSSOP-14
文件頁數(shù): 12/24頁
文件大小: 898K
代理商: SN74LV125APWG4
SN54LV125A, SN74LV125A
QUADRUPLE BUS BUFFER GATES
WITH 3STATE OUTPUTS
SCES124L DECEMBER 1997 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
L
LL
H
X
Z
logic diagram (positive logic)
2A
2Y
2OE
1A
1Y
1OE
1
2
4
5
3
6
4A
4Y
4OE
3A
3Y
3OE
10
9
13
12
8
11
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
相關(guān)PDF資料
PDF描述
SN74LV125ATDBRE4 LV/LV-A/LVX/H SERIES, 4-BIT DRIVER, TRUE OUTPUT, PDSO14
SN74LV125ATRGYRG4 LV/LV-A/LVX/H SERIES, 4-BIT DRIVER, TRUE OUTPUT, PQCC14
SN74LV125ATNS LV/LV-A/LVX/H SERIES, 4-BIT DRIVER, TRUE OUTPUT, PDSO14
SN74LV125ATPWTG4 LV/LV-A/LVX/H SERIES, 4-BIT DRIVER, TRUE OUTPUT, PDSO14
SN74LV138APWLE LV/LV-A/LVX/H SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
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