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參數(shù)資料
| 型號： | SN74LS256D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | >6V Fixed Gain, High Dynamic Range Amplifier |
| 中文描述： | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SN74LS256D |
5-421
FAST AND LS TTL DATA
DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A0, A1), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q0–Q3).
When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs
(Q0–Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and
E are both LOW. When CL is HIGH and E is LOW, the selected output
(Q0–Q3), determined by the Address inputs, follows D. When the E goes
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E=LOW, CL=HIGH), changing more than one bit of the Address
(A0, A1) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E=CL=HIGH).
Serial-to-Parallel Capability
Output From Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Active Low Common Clear
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING
(Note a)
HIGH
LOW
A0, A1
Da, Db
E
CL
Q0a–Q3a,
Q0b–Q3b
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
μ
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
Address Inputs
Data Inputs
Enable Input (Active LOW)
Clear Input (Active LOW)
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
Parallel Latch Outputs (Note b)
10 U.L.
5 (2.5) U.L.
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LATCH
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LS256N | >6V Fixed Gain Amp, High Gain, Minimum Feedback |
| SN54LS259 | Octal Bidirectional Transceiver with 3-State Inputs/Outputs; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500 |
| SN54LS259J | Octal Bidirectional Transceiver with 3-State Inputs/Outputs; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000 |
| SN74LS259D | 8-BIT ADDRESSABLE LATCH |
| SN74LS259N | 8-BIT ADDRESSABLE LATCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS256J | 制造商:Motorola Inc 功能描述: |
| SN74LS256N | 制造商:Motorola Inc 功能描述:Latch, Dual, 4 Bit, 16 Pin, Plastic, DIP |
| SN74LS257AJD | 制造商:Motorola Inc 功能描述:LOGIC MUX, QUAD, 2-INPUT, LS-TTL, 16 Pin, Ceramic, DIP |
| SN74LS257AJDS | 制造商:Motorola Inc 功能描述:LOGIC MUX, QUAD, 2-INPUT, LS-TTL, 16 Pin, Ceramic, DIP |
| SN74LS257AN | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:LOGIC MUX, QUAD, 2-INPUT, LS-TTL, 16 Pin, Plastic, DIP 制造商:Texas Instruments 功能描述:LOGIC MUX, QUAD, 2-INPUT, LS-TTL, 16 Pin, Plastic, DIP |
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