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參數(shù)資料
| 型號： | SN74LS195ADR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 213K |
| 代理商： | SN74LS195ADR2 |
SN74LS195A
http://onsemi.com
3
LOGIC DIAGRAM
J
P
0
P
1
P
2
P
3
CP
PE
K
MR
Q
0
Q
0
Q
1
Q
3
R
CP
S
C
D
Q
0
Q
2
Q
3
14
1
2
6
7
3
4
5
9
11
12
10
13
15
CC
= PIN 16
V
= PIN NUMBERS
R
CP
S
C
D
Q
0
R
CP
S
C
D
Q
2
Q
3
R
CP
S
C
D
Q
3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS195A 4-Bit Shift
Register. The device is useful in a wide variety of shifting,
counting and storage applications. It performs serial,
parallel, serial to parallel, or parallel to serial data transfers
at very high speeds.
The LS195A has two primary modes of operation, shift
right (Q
0
Q
1
) and parallel load which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is
HIGH, serial data enters the first flip-flop Q
0
via the J and
K inputs and is shifted one bit in the direction Q
0
Q
2
Q
3
following each LOW to HIGH clock transition.
The JK inputs provide the flexibility of the JK type input for
special applications, and the simple D type input for general
applications by tying the two pins together. When the PE
Q
1
input is LOW, the LS195A appears as four common clocked
D flip-flops. The data on the parallel inputs P
0
, P
1
, P
2
, P
3
is
transferred to the respective Q
0
, Q
1
, Q
2
, Q
3
outputs
following the LOW to HIGH clock transition. Shift left
operations (Q
3
Q
2
) can be achieved by tying the Q
n
Outputs to the P
n
1
inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since
the LS195A utilizes edge-triggering, there is no restriction
on the activity of the J, K, P
n
and PE inputs for logic
operation — except for the set-up and release time
requirements.
A LOW on the asynchronous Master Reset (MR) input
sets all Q outputs LOW, independent of any other input
condition.
MODE SELECT — TRUTH TABLE
OPERATING MODES
INPUTS
OUTPUTS
MR
PE
J
K
P
n
Q
0
Q
1
Q
2
Q
3
Q
3
Asynchronous Reset
L
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
Shift, Reset First
Shift, Toggle First Stage
Shift, Retain First Stage
Parallel Load
H
H
H
H
H
h
h
h
h
I
h
I
h
I
X
h
I
I
h
X
X
X
X
X
p
n
H
L
q
0
q
0
p
0
q
0
q
0
q
0
q
0
p
1
q
1
q
1
q
1
q
1
p
2
q
2
q
2
q
2
q
2
p
3
q
2
q
2
q
2
q
2
p
3
L = LOW voltage levels
H = HIGH voltage levels
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
p
n
(q
n
) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
HIGH clock transition.
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PDF描述 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS195AJ | 制造商:Motorola Inc 功能描述: |
| SN74LS195AN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74LS195AN3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS195AN84 | 制造商:Motorola 功能描述:74LS195N |
| SN74LS195AND | 制造商:Motorola Inc 功能描述:Shift Register, 16 Pin, Plastic, DIP |
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