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參數(shù)資料
| 型號(hào)： | SN74LS16N |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 門電路 |
| 英文描述： | LS SERIES, HEX 1-INPUT INVERT GATE, PDIP14 |
| 封裝： | PLASTIC, MS-001AA, DIP-14 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 641K |
| 代理商： | SN74LS16N |
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SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPENCOLLECTOR HIGHVOLTAGE OUTPUTS
SDLS020E MAY 1990 REVISED FEBRUARY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPHL
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO ≈ 50 , tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
≈1.5 V
VOH 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V
tw
1.3 V
VOL
VOH
Figure 1. Load Circuits and Voltage Waveforms
The SN74LS16 is obsolete
and is no longer supplied.
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| SN74LS06DRG4 | LS SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
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| SN74LS170 WAF | 制造商:ON Semiconductor 功能描述: |
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| SN74LS173AD | 功能描述:觸發(fā)器 4-Bit D-type Reg With 3-State Outputs RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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