參數(shù)資料
型號: SN74LS148NE4
廠商: TEXAS INSTRUMENTS INC
元件分類: 算術(shù)邏輯單元
英文描述: LS SERIES, 8-BIT ENCODER, INVERTED OUTPUT, PDIP16
封裝: ROHS COMPLIANT, PLASTIC, DIP-16
文件頁數(shù): 5/26頁
文件大?。?/td> 831K
代理商: SN74LS148NE4
SN54147, SN54148, SN54LS147, SN54LS148
SN74147, SN74148 (TIM9907), SN74LS147, SN74LS148
10LINE TO 4LINE AND 8LINE TO 3LINE PRIORITY ENCODERS
SDLS053B OCTOBER 1976 REVISED MAY 2004
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
0 1
23
4
5
67 EI
EO
A0
A1
A2 GS
’148/’LS148
0 1
23
4
5
67 EI
EO
A0
A1
A2
GS
’148/LS148
’08/’LS08
0 1
23
4
5
67
9 10 11 12 13 14 15
Enable
(active low)
01
2
3
Encoded Data (active low)
Priority Flag
(active low)
16-Line Data (active low)
0 1
23
4
5
67 EI
EO A0
A1
A2 GS
’148/’LS148
0 1
23
4
5
67 EI
EO
A0
A1
A2
GS
’148/’LS148
’HC00
0 1
2 3
4
5
6 7
8 9 10 11 12 13 14 15
Enable
(active low)
01
2
3
Encoded Data (active high)
Priority Flag
(active high)
16-Line Data (active low)
8
Figure 3. Priority Encoder for 16 Bits
Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear
during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient
low on GS when all inputs are high. This must be considered when strobing the outputs.
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