參數(shù)資料
型號: SN74LS125AN8
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LS SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDIP14
封裝: ROHS COMPLIANT, PLASTIC, MS-001AA, DIP-14
文件頁數(shù): 20/21頁
文件大?。?/td> 781K
代理商: SN74LS125AN8
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO ≈ 50 , tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V
tw
1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
相關(guān)PDF資料
PDF描述
SN74LS126ANSRG4 LS SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
SN74LS126ADRE4 LS SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
SN74LS145NSR LS SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16
SNJ54LS145J LS SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, CDIP16
SN74LS145DG4 LS SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LS125AN84 制造商:Motorola 功能描述:74LS125N SB-12
SN74LS125AND 制造商:ONS 功能描述:ON SEMICONDUCTORN NXC7D
SN74LS125ANDS 制造商:Motorola Inc 功能描述:Driver/Buffer Device, Single, 4-Bit, 14 Pin, Plastic, DIP
SN74LS125ANE4 功能描述:緩沖器和線路驅(qū)動器 Quad Bus Buffer With 3-State Outputs RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
SN74LS125ANG4 制造商:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER 74LC125 DIP