參數(shù)資料
型號(hào)： SN74HCT74PWG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： GREEN, PLASTIC, TSSOP-14
文件頁數(shù)： 13/19頁
文件大?。?/td> 811K
代理商： SN74HCT74PWG4
SN54HCT74, SN74HCT74
DUAL DTYPE POSITIVEEDGETRIGGERED FLIPFLOPS
WITH CLEAR AND PRESET
SCLS169E DECEMBER 1982 REVISED APRIL 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT74
SN74HCT74
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/v
Input transition rise/fall time
500
ns
TA
Operating free-air temperature
55
125
40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
SN54HCT74
SN74HCT74
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = 20 A
4.5 V
4.4
4.499
4.4
V
VOH
VI = VIH or VIL
IOH = 4 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI = VIH or VIL
IOL = 20 A
4.5 V
0.001
0.1
V
VOL
VI = VIH or VIL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
VI = VCC or 0
5.5 V
±0.1
±100
±1000
nA
ICC
VI = VCC or 0,
IO = 0
5.5 V
4
80
40
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
4.5 V
to 5.5 V
3
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
SN54HCT74
SN74HCT74
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
4.5 V
27
18
22
MHz
fclock
Clock frequency
5.5 V
30
20
24
MHz
PRE or CLR low
4.5 V
16
24
20
tw
Pulse duration
PRE or CLR low
5.5 V
14
21
18
ns
tw
Pulse duration
CLK high or low
4.5 V
18
27
23
ns
CLK high or low
5.5 V
16
24
21
Data
4.5 V
12
18
15
tsu
Setup time before CLK
↑
Data
5.5 V
11
16
14
ns
tsu
Setup time before CLK
↑
PRE or CLR inactive
4.5 V
0
ns
PRE or CLR inactive
5.5 V
0
th
Hold time, data after CLK
↑
4.5 V
0
ns
th
Hold time, data after CLK
↑
5.5 V
0
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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