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參數(shù)資料
| 型號： | SN74HCT377NE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-001AD, DIP-20 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 458K |
| 代理商： | SN74HCT377NE4 |
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
1.3 V
0.3 V
2.7 V
3 V
0 V
tr
tf
Reference
Input
Data
Input
1.3 V
High-Level
Pulse
1.3 V
3 V
0 V
1.3 V
3 V
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
10%
90%
3 V
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
1.3 V
tPLH
tPHL
1.3 V
10%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-
Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤ 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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