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參數(shù)資料
| 型號： | SN74HC652DWE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | GREEN, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 449K |
| 代理商： | SN74HC652DWE4 |
SN54HC652, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS151E – DECEMBER 1982 – REVISED MARCH 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
OPERATION OR FUNCTION
L
H
H or L
X
Input
Isolation
L
H
↑↑
X
Input
Store A and B data
X
H
↑
H or L
X
Input
Unspecified
Store A, hold B
H
↑↑
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified
Input
Hold A, store B
L
↑↑
XX
Output
Input
Store B in both registers
L
X
L
Output
Input
Real-time B data to A bus
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
X
L
X
Input
Output
Real-time A data to B bus
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions are enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled;
i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74HC652DWG4 | 功能描述:總線收發(fā)器 Octal Bus Transceivr And Registers RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74HC652DWR | 功能描述:總線收發(fā)器 Octal Bus Trncvr/Reg W/3-State Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74HC652DWRE4 | 功能描述:總線收發(fā)器 Octal Bus Trncvr/Reg W/3-State Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74HC652DWRG4 | 功能描述:總線收發(fā)器 Octal Bus Transceivr And Registers RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74HC652NT | 功能描述:總線收發(fā)器 Tri-State Octal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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