參數(shù)資料
型號(hào): SN74HC163PWR
廠商: TEXAS INSTRUMENTS INC
元件分類: 計(jì)數(shù)器
英文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 12/28頁
文件大?。?/td> 894K
代理商: SN74HC163PWR
SN54HC163, SN74HC163
4BIT SYNCHRONOUS BINARY COUNTERS
SCLS298D JANUARY 1996 REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
相關(guān)PDF資料
PDF描述
SN74HC163N HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
SN74HC163DBR HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SN74HC164NE4 HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14
SN74HC164NSR HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
SN74HC164DT HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
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