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參數(shù)資料
| 型號： | SN74BCT8374ADWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | BCT/FBT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SN74BCT8374ADWRG4 |
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SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E – JUNE 1990 – REVISED JULY 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
DESCRIPTION
CLK
Normal-function clock input. See function table for normal-mode logic. An internal pullup forces CLK to a high level if left
unconnected.
1D–8D
Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.
GND
Ground
OE
Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level
if left unconnected.
1Q–8Q
Normal-function data outputs. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset
signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS.
VCC
Supply voltage
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74BCT8374ANT | 功能描述:觸發(fā)器 Device w/Octal D-Typ Edge-Trig Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74BCT8374ANTE4 | 功能描述:特定功能邏輯 Device w/Octal D-Typ Edge-Trig Flip-Flop RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74BCT8374NT | 制造商:Texas Instruments 功能描述:Flip Flop, Octal, D Type, 24 Pin, Plastic, DIP |
| SN74BCT899DW | 制造商:Texas Instruments 功能描述: |
| SN74CB373384DBQR | 制造商:Texas Instruments 功能描述: |
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