參數(shù)資料
型號: SN74AVCH8T245DGVR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: GREEN, TVSOP-24
文件頁數(shù): 12/22頁
文件大?。?/td> 561K
代理商: SN74AVCH8T245DGVR
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES565G – APRIL 2004 – REVISED MARCH 2007
The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH8T245 is designed so the control pins (DIR and OE) are supplied by VCCA.
The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a '245
function, with minimal printed circuit board redesign.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
L
B data to A bus
L
H
A data to B bus
H
X
All output Hi-Z
LOGIC DIAGRAM (POSITIVE LOGIC)
2
相關(guān)PDF資料
PDF描述
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