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參數(shù)資料
| 型號(hào)： | SN74AVCH1T45YEPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | AVC SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, BGA6 |
| 封裝： | DSBGA-6 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 458K |
| 代理商： | SN74AVCH1T45YEPR |
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1
VCC2
SYSTEM-1
SYSTEM-2
DIR CTRL
I/O-1
I/O-2
VCC2
STATE
DIR CTRL
I/O-1
DESCRIPTION
1
2
3
4
H
L
Out
HiZ
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1
and I/O-2 are disabled. The bus-line state depends on bus hold.
DIR bit is flipped. I/O-1 and I/O02 still are disabled. The bus-line
state depends on bus hold.
I/O-2
HiZ
Out
In
HiZ
In
SYSTEM-2 data to SYSTEM-1
Enable Times
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598C – JULY 2004 – REVISED OCTOBER 2005
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 13. Bidirectional Logic Level-Shifting Application
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
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| SN74AVCH1T45YZPR | 功能描述:轉(zhuǎn)換 - 電壓電平 SnglBDualSplyBusTrns w/CnfgrbleVltg RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74AVCH20T245GR | 功能描述:轉(zhuǎn)換 - 電壓電平 20BDUALSplyBUSTrnsw/ CnfgrbleVltgTRNSLTN RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74AVCH20T245KR | 功能描述:總線收發(fā)器 20B DUAL SUPPLY Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74AVCH20T245VR | 功能描述:轉(zhuǎn)換 - 電壓電平 20B DUAL SUPPLY Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74AVCH24T245GRGR | 功能描述:轉(zhuǎn)換 - 電壓電平 24B Dual-Supply Bus Trans RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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