參數資料
型號: SN74AVCH125DGVR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AVC SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: TVSOP-14
文件頁數: 12/12頁
文件大?。?/td> 149K
代理商: SN74AVCH125DGVR
www.ti.com
PRODUCT
PREVIEW
PARAMETER MEASUREMENT INFORMATION
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
× VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH 0.15 V
0 V
VCC
0 V
tw
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
× VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
tPLH
2
× VCC
VCC
SN74AVCH125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES254C – APRIL 1999 – REVISED NOVEMBER 2005
V
CC = 2.5 V ± 0.2 V
Figure 4. Load Circuit and Voltage Waveforms
9
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