參數(shù)資料
型號(hào)： SN74AVC1T45YEPR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 總線收發(fā)器
英文描述： AVC SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PBGA6
封裝： DSBGA-6
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 494K
代理商： SN74AVC1T45YEPR
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1
VCC2
SYSTEM-1
SYSTEM-2
DIR CTRL
I/O-1
I/O-2
Pullup/Pulldown
or Bus Hold
VCC2
Pullup/Pulldown
or Bus Hold
Enable Times
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530E – DECEMBER 2003 – REVISED JUNE 2006
Figure 3 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
2
H
Hi-Z
bus-line state depends on pullup or pulldown.(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
3
L
Hi-Z
pulldown.(1)
4
L
Out
In
SYSTEM-2 data to SYSTEM-1
(1)
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74AVC1T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74AVC1T45YZPR 功能描述:轉(zhuǎn)換 - 電壓電平 Single-Bit Dual Supply Bus Trans RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
SN74AVC1T45YZTR 功能描述:轉(zhuǎn)換 - 電壓電平 Sgl Bit Dual-Supply Bus Xcvr RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
SN74AVC20T245DGG 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
SN74AVC20T245DGGR 功能描述:轉(zhuǎn)換 - 電壓電平 20B Dual Supply Bus Xceiver RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
SN74AVC20T245DGVR 功能描述:轉(zhuǎn)換 - 電壓電平 20-Bit Dual Supply Bus Transceiver RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
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