參數(shù)資料
型號(hào)： SN74AVC1T45DRLRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： AVC SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6
封裝： GREEN, PLASTIC, SOT-553, SOP-6
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 909K
代理商： SN74AVC1T45DRLRG4
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1
VCC2
SYSTEM-1
SYSTEM-2
DIR CTRL
I/O-1
I/O-2
Pullup/Pulldown
or Bus Hold
VCC2
Pullup/Pulldown
or Bus Hold
Enable Times
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Figure 3 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
2
H
Hi-Z
bus-line state depends on pullup or pulldown.(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
3
L
Hi-Z
pulldown.(1)
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
(1)
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74AVC1T45 using the following formulas:
t
PZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
t
PZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
t
PZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
t
PZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
Copyright 2003–2008, Texas Instruments Incorporated
15
Product Folder Link(s): SN74AVC1T45
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