參數(shù)資料
型號: SN74AUP3G34RSER
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, QCC8
封裝: QFN-8
文件頁數(shù): 16/18頁
文件大小: 716K
代理商: SN74AUP3G34RSER
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
1 M
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPLH
VOH
VOL
VI
0 V
Input
Output
VM
5, 10, 15, 30 pF
VCC/2
VCC
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
CL
VM
VI
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
th
tsu
Data Input
Timing Input
VCC
0 V
VCC
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2
VCC
VCC/2
www.ti.com
SCES766B – DECEMBER 2009 – REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , for
propagation delays tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Copyright 2009–2010, Texas Instruments Incorporated
7
Product Folder Link(s): SN74AUP3G34
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