參數(shù)資料
型號: SN74AUP3G17YFPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: AUP/ULP/V SERIES, TRIPLE 1-INPUT INVERT GATE, PBGA8
封裝: 0.20 MM, LEAD FREE, WCSP-8
文件頁數(shù): 19/19頁
文件大?。?/td> 717K
代理商: SN74AUP3G17YFPR
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 xVCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH - V
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2 x VCC
GND
TEST
S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 k
2 x VCC
www.ti.com
SCES765B – DECEMBER 2009 – REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr/tf = 3 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPLH and tPHL are the same as tpd.
G.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
Copyright 2009–2010, Texas Instruments Incorporated
9
Product Folder Link(s): SN74AUP3G17
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