參數(shù)資料
型號(hào)： SN74AUP2G80RSER
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC8
封裝： QFN-8
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 725K
代理商： SN74AUP2G80RSER
C
C
TG
C
TG
C
CLK
D
Q
C
TG
SCES756A – DECEMBER 2009 – REVISED MARCH 2010
www.ti.com
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting
the levels at the outputs.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP2G80YFPR
_ _ _ H X _
0.23-mm Large Bump – YFP (Pb-free)
uQFN – DQE
Reel of 5000
SN74AUP2G80DQER
PU
–40°C to 85°C
QFN – RSE
Reel of 5000
SN74AUP2G80RSER
PU
SSOP – DCU
Reel of 3000
SN74AUP2G80DCUR
H80_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
↑
H
L
↑
L
H
L
X
Q0
LOGIC DIAGRAM (POSITIVE LOGIC)
Pin numbers shown are for the DCU and DQE packages.
2
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP2G80
相關(guān)PDF資料
PDF描述
SN74AUP3G06DCUR AUP/ULP/V SERIES, TRIPLE 1-BIT DRIVER, INVERTED OUTPUT, PDSO8
SN74AUP3G17YFPR AUP/ULP/V SERIES, TRIPLE 1-INPUT INVERT GATE, PBGA8
SN74AUP3G34RSER AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, QCC8
SN74AUP3G34YFPR AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PBGA8
SN74AVC126DR AVC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74AUP2G80YFPR 功能描述:觸發(fā)器 Low-Pwr Dual Pos- Edge-Trgd D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74AUP3G04DCUR 功能描述:緩沖器和線路驅(qū)動(dòng)器 Low-Power Triple Inverter Gate RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
SN74AUP3G04DCUR 制造商:Texas Instruments 功能描述:Inverter Logic IC 制造商:Texas Instruments 功能描述:IC, TRIPLE INVERTER, US8
SN74AUP3G04DQER 功能描述:緩沖器和線路驅(qū)動(dòng)器 Low-Power Triple Inverter Gate RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
SN74AUP3G04RSER 功能描述:變換器 Lo-Pwr Trpl Inverter Gate RoHS:否 制造商:NXP Semiconductors 電路數(shù)量:6 邏輯系列:74ABT 邏輯類型:BiCMOS 高電平輸出電流:- 15 mA 低電平輸出電流:20 mA 傳播延遲時(shí)間:2.2 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 工作溫度范圍: 封裝 / 箱體:DIP-14 封裝:Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*