參數(shù)資料
型號(hào)： SN74AUP2G126YZPR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 總線收發(fā)器
英文描述： AUP/ULP/V SERIES, 2-BIT DRIVER, TRUE OUTPUT, PBGA8
封裝： GREEN, DSBGA-8
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 814K
代理商： SN74AUP2G126YZPR
AUP
LVC
AUP
LVC
Static-PowerConsumption
(mA)
Dynamic-PowerConsumption
(pF)
Single,dual,andtriplegates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time-ns
V
o
lt
a
g
e
-
V
AUP1G08dataatC =15pF
L
Output
Input
SwitchingCharacteristics
at25MHz
SCES687D – JANUARY 2007 – REVISED DECEMBER 2009
www.ti.com
Figure 1. AUP – The Lowest Power Family
Figure 2. Excellent Signal Integrity
The SN74AUP2G126 is a dual bus driver/line driver with 3-state outputs, designed for 0.8-V to 3.6-V VCC
operation. The outputs are disabled when the associated output-enable (OE) input is low. This device has the
input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP2G126YFPR
_ _ _ HN_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP2G126YZPR
_ _ _ HN_
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
uQFN – DQE
Reel of 5000
SN74AUP2G126DQER
PW
QFN – RSE
Reel of 5000
SN74AUP2G126RSER
HN
VSSOP – DCU
Reel of 3000
SN74AUP2G126DCUR
H26_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
DCU: The actual top-side marking has one additional character to designate the wafer fab/assembly site.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
X(1)
Z
(1)
Floating inputs allowed
2
Copyright 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP2G126
相關(guān)PDF資料
PDF描述
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SN74AUP2G80DCUR AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
SN74AUP2G80RSER AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC8
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SN74AUP2G14DSF2 功能描述:變換器 Low-Pwr Dual Schmitt Trigger Inverter RoHS:否 制造商:NXP Semiconductors 電路數(shù)量:6 邏輯系列:74ABT 邏輯類(lèi)型:BiCMOS 高電平輸出電流:- 15 mA 低電平輸出電流:20 mA 傳播延遲時(shí)間:2.2 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 工作溫度范圍: 封裝 / 箱體:DIP-14 封裝:Tube
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