參數(shù)資料
型號(hào): SN74AUP1G80DBVRE4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 鎖存器
英文描述: AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5
封裝: GREEN, PLASTIC, SOT-23, 5 PIN
文件頁(yè)數(shù): 12/25頁(yè)
文件大?。?/td> 974K
代理商: SN74AUP1G80DBVRE4
AUP
LVC
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at C
L = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
D
CLK
Q
CLK
D
Q
SCES593E – JULY 2004 – REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE PART
TOP-SIDE
TA
PACKAGE(2)
NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G80YFPR
_ _ _HX_
0.23-mm Large Bump – YFP
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G80YZPR
_ _ _HX_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G80DRYR
HX
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G80DSFR
HX
Reel of 3000
SN74AUP1G80DBVR
SOT (SOT-23) – DBV
H80_
Reel of 250
SN74AUP1G80DBVT
Reel of 3000
SN74AUP1G80DCKR
SOT (SC-70) – DCK
HX_
Reel of 250
SN74AUP1G80DCKT
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
H
L
L
H
L or H
X
Q 0
LOGIC DIAGRAM (POSITIVE LOGIC)
2
Copyright 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G80
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SN74AUP1G80DBVTE4 功能描述:觸發(fā)器 Lo PWR SNGL Pos Edge Trgrd DType FlipFlop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類(lèi)型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類(lèi)型:CMOS 輸出類(lèi)型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
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