參數(shù)資料
型號: SN74AUP1G17MDCKREP
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO5
封裝: GREEN, PLASTIC, SC70, 5 PIN
文件頁數(shù): 5/12頁
文件大?。?/td> 314K
代理商: SN74AUP1G17MDCKREP
www.ti.com
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at C
L = 15 pF
Switching Characteristics
at 25 MHz
Output
Input
AUP
LVC
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
SCES684 – JANUARY 2007
xxxxxx
Figure 2. Excellent Signal Integrity
Figure 1. AUP - The Lowest-Power Family
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching noise immunity at the input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
–55
°C to 125°C SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G17MDCKREP
BZU
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCK: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to
designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
2
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