參數(shù)資料
型號: SN74AUP1G08YEPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: 74AUP1G SERIES, 2-INPUT AND GATE, BGA5
封裝: WCSP-5
文件頁數(shù): 7/14頁
文件大?。?/td> 343K
代理商: SN74AUP1G08YEPR
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
This single 2-input positive-AND gate performs the Boolean function Y + A B or Y + A ) B in positive logic.
1
2
4
A
B
Y
SN74AUP1G08
LOW-POWER SINGLE 2-INPUT POSITIVE-AND GATE
SCES502D – NOVEMBER 2003 – REVISED JUNE 2005
Figure 2. Excellent Signal Integrity
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar – WCSP (DSBGA)
Tape and reel
SN74AUP1G08YEPR
0.23-mm Large Bump – YEP
_ _ _HE_
NanoFree – WCSP (DSBGA)
Tape and reel
SN74AUP1G08YZPR
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SOT (SOT-23) – DBV
Tape and reel
SN74AUP1G08DBVR
H08_
SOT (SC-70) – DCK
Tape and reel
SN74AUP1G08DCKR
HE_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G08DRLR
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
H
L
H
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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相關代理商/技術參數(shù)
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