參數(shù)資料
型號: SN74AUP1G06DRLRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: AUP/ULP/V SERIES, 1-INPUT INVERT GATE, PDSO5
封裝: GREEN, PLASTIC, SOT-553, 5 PIN
文件頁數(shù): 17/23頁
文件大?。?/td> 1024K
代理商: SN74AUP1G06DRLRG4
www.ti.com
SCES590D – JULY 2004 – REVISED MAY 2010
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range(2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
4.6
V
VO
Output voltage range in the high or low state(2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
DBV package
206
DCK package
252
qJA
Package thermal impedance(3)
DSF package
300
°C/W
DRY package
234
YFP package
132
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright 2004–2010, Texas Instruments Incorporated
3
Product Folder Link(s): SN74AUP1G06
相關(guān)PDF資料
PDF描述
SN74AUP1G07DSFR AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO6
SN74AUP1G07DCKTE4 AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO5
SN74AUP1G07YEPR AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PBGA5
SN74AUP1G08DBVRE4 AUP/ULP/V SERIES, 2-INPUT AND GATE, PDSO5
SN74AUP1G08YEPR 74AUP1G SERIES, 2-INPUT AND GATE, BGA5
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