參數(shù)資料
型號(hào)： SN74ALVC7813DL
廠商： Texas Instruments, Inc.
英文描述： 64 】 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
中文描述： 64】18 LOW-POWER時(shí)鐘先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 1/14頁(yè)
文件大?。?/td> 192K
代理商： SN74ALVC7813DL
SN74ALVC7813
64
×
18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS594A – OCTOBER 1997 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
Low-Power Advanced CMOS Technology
Operates From 3-V to 3.6-V V
CC
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
Read and Write Operations Synchronized
to Independent System Clocks
Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width
Expansion Without Additional Logic
Input-Ready Flag Synchronized to Write
Clock
Output-Ready Flag Synchronized to Read
Clock
Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 50 MHz
Pin-to-Pin Compatible With SN74ACT7803,
SN74ACT7805, and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Lead Spacing
description
The SN74ALVC7813 is suited for buffering
asynchronous data paths up to 50-MHz clock
rates and 13-ns access times. This device is
designed for 3-V to 3.6-V V
CC
operation. Two
devices can be configured for bidirectional data
buffering without additional logic.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO
must be reset upon power up.
The SN74ALVC7813 is characterized for operation from 0
°
C to 70
°
C.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
IR
OE1
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR
DL PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
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SN74ALVC7814-40DLR 功能描述:先進(jìn)先出 64 x 18 3.3-V ASynch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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